There has been proposed an embodiment in which chips different in performance are mixedly mounted on one package for the purpose of higher density and higher performance of a semiconductor package. In this case, a cost advantageous technology for high density interconnect between the chips is important (e.g., see Patent Literature 1).
A package-on-package technology for connecting different packages which are stacked on a package by flip-chip mounting has been widely applied to a smartphone and a tablet terminal (e.g., see non-Patent Literature 1 and non-Patent Literature 2).
Further, there has been proposed, as another form of mounting a plurality of chips at higher density, a packaging technology using an organic substrate having a high density wiring (organic interposer), a fan-out packaging technology (FO-WLP) having a through mold via (TMV), a packaging technology using a silicon interposer or a grass interposer, a packaging technology using a through-silicon via (TSV), a packaging technology using a chip embedded in a substrate for inter-chip transmission, or the like.
Particularly, in the organic interposer and the FO-WLP, in a case where the semiconductor chips are mounted in parallel with each other, a micro wiring layer is required in order to make the semiconductor chips electrically conduct with each other at a high density (e.g., see Patent Literature 2).